This article introduces the rate compatibility of the host interface and network cable interface of the 10GbE SFP module based on Marvell 88X3310 program.
1. Host Interface
      The host interface of the 88X3310-based 10GbE SFP module is set to 10G XFI mode, and the rate of the host interface is not adaptable to other rates, so the 10GbE interface of the 88X3310-based 10GbE SFP module can only be used on switch ports that have been set to 10G rate beforehand, or it will not work properly.
2. Network cable interface
      When the 10GbE SFP module of 88X3310 solution is interconnected (RJ45 port)
 with the other module, it can be compatible with 10/100/1000M/2.5G/5G/10G, and the rate will be automatically adjusted according to the rate of the port on the other end. When the port rate of the other end is fixed 10G, it will adapt to 10G, when the port rate of the other end is fixed 1G, it will adapt to 1G, and other rates are similar. When the other end port is multi-rate adaptive, it will adapt to the highest rate achievable at both ends. Thus, the module can be used flexibly in a variety of Ethernet environments.

Block diagram of the Marvell 88X3310 solution with multi-rate compatibility

Figure 1 Block diagram of the Marvell 88X3310 solution with multi-rate compatibility

      ▪ The network interface supports 10GBase-T 10G rate with a transmission distance of up to 30m over Cat 6A cable.
      ▪ The network interface supports 5GBase-T rate with a transmission distance of up to 70m over Cat 5E cable.
      ▪ The network cable interface supports 2.5GBase-T rate, and the transmission distance is up to 100m via Cat 5E cable.
      ▪ The network cable interface supports 10/100/1000Base-T rate, and the transmission distance is up to 100m via Cat 5E cable.
3. Flow Control
      When the 88X3310 solution's 10GbE interface works at 10G rate, the rate of both sides of the chip (host side and cable side) is 10G, and there is no rate conversion or flow control problem.
      When the cable side of the adaptive rate of 10G or less, because the host side is still working at 10G rate, at this time, the rate of the two sides of the chip is not consistent, therefore, the chip needs to be converted to the internal rate. The following 2.5G rate as an example of how the chip is flow control.

88X3310 program flow control block diagram

Figure 2 88X3310 program flow control block diagram

      As shown in the figure above, in the receive direction, 88X3310 receives the data sent from the other end at a rate of 2.5G, 88X3310 sends to the host MAC at a rate of 10G, the receive rate is much lower than the send rate, therefore, there is no frame overflow, no need for flow control.
      In the sending direction, the host MAC sends to the 88X3310 at a rate of 10G, and the 88X3310 sends to the peer at a rate of 2.5G, and during this process, there will be frame overflow if no flow control is performed. At this point, the 88X3310 will enable an internal 16KB FIFO buffer. Since the receiving rate is much higher than the transmitting rate, the FIFO buffer will soon fill up and overflow. In order to prevent this from happening, the host MAC needs to insert a certain number of blank frames into the middle of the transmitted data frames, and when the 88X3310 receives the blank frames, it will discard them, and put the useful frames into the buffer, so when the number of blank frames inserted is just the right number, the smooth transmission of data can be ensured. The number of blank frames is related to the wire side rate and the frame length, you need to refer to the datasheet of 88X3310 for details.
      In practice, the host MAC does not insert the appropriate number of blank frames according to the requirements of the 88X3310 datasheet, and then there will be a cache overflow, resulting in lower transmission efficiency, which is manifested in the form of the network side of the link to the 2.5G rate, but the measured bandwidth is lower than 2.5G.
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